Frequency selection granularity for integrated circuits
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United States of America Patent
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May 17, 2016
Grant Date -
Mar 13, 2014
app pub date -
Dec 28, 2012
filing date -
Sep 12, 2012
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Abstract
Clock signal generation circuitry. A frequency multiplier is coupled to receive a clock signal and to generate a frequency-multiplied clock signal. A switching circuit is coupled to receive at least two reference clock signals. The switching circuit provides one of the reference clock signals in response to a reference select signal. A phase locked loop (PLL) is coupled to receive the frequency-multiplied clock signal and the selected reference clock signal. The PLL generates an output clock signal.
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