Importance

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Abstract

A semiconductor storage device has a cell array, a redundant array provided logically separated from the cell array, a cache memory having a storing area of data read from or written in the cell array by one access, defective column storage to store a column address of a defective column in the cell array, a defective column determination module to determine whether a column address to be accessed matches the column address stored in the defective column storage, and a clock generator to generate a clock for accessing each of the divided areas for each period of the interleave access and, when the defective column determination module determines that there is a match, instead of a clock accessing a divided page buffer area at the generation timing of the clock accessing the divided page buffer area.

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First Claim