Digital frequency-locked loop with reference clock error detection
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United States of America Patent
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May 17, 2016
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N/A
app pub date -
May 22, 2015
filing date -
May 22, 2015
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Abstract
The present disclosure is directed to a system and method for generating an output oscillating signal using an input oscillating signal that is subject to missing pulses and/or distortions. The output oscillating signal can be generated at a desired frequency by a frequency-locked loop (FLL) that uses the input oscillating signal as a reference clock. Because the input oscillating signal is used as a reference clock, missing pulses and/or distortions in the input oscillating signal can adversely affect the continued, stable generation of the output oscillating signal. To this end, the system and method of the present disclosure use an input oscillating signal error detector to open the FLL upon detecting a missing pulse in the input oscillating signal and/or a distortion in the input oscillating signal.
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