Method and system of synchronizing processors to the same computational point
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United States of America Patent
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May 24, 2016
Grant Date -
Jul 9, 2015
app pub date -
Apr 17, 2014
filing date -
Jan 8, 2014
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Abstract
A system for synchronizing central processing units (CPU) includes a schedule module that communicates a synchronization point, a first CPU that writes a first memory address to a first register in response to the first CPU reaching the synchronization point, and a second CPU that writes a second memory address to a second register in response to the second CPU reaching the synchronization point. The system further includes a first logical AND module that writes a first value to a third register based on the first and second memory addresses and a second logical AND module that writes a second value to a fourth register based on the first and second memory addresses. The system also includes a scheduler module that selectively generates a processor sync signal based on the first and second value.
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