Detecting and managing bad columns
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United States of America Patent
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May 24, 2016
Grant Date -
N/A
app pub date -
Oct 9, 2013
filing date -
Oct 9, 2013
priority date (Note) -
In Force
status (Latency Note)
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Abstract
A system, computer readable medium and a method. The system includes a memory controller that comprises a control circuit and an interface. The memory controller is arranged to receive or generate bad columns information indicative of bad columns of the NAND flash memory array; wherein the bad columns information has a column resolution. The memory controller is arranged to receive an input data unit to be written to the NAND flash memory array; wherein the input data unit comprises bad column mapped data bits that are mapped to flash memory cells that belong to bad columns of the NAND flash memory array. The interface is arranged to send the input data unit to the NAND flash memory unit; instruct the NAND flash memory unit to write the input data unit to a first portion of the NAND flash memory array to provide a programmed data unit; send the bad column mapped data bits to the NAND flash memory unit; and instruct the NAND flash memory unit to write the bad column mapped data bits to a second portion of the NAND flash memory array to provide programmed bad column mapped data bits.
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