Aspect ratio trapping and lattice engineering for III/V semiconductors

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United States of America Patent

PATENT NO 9349809
SERIAL NO

14541179

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A method of forming a semiconductor structure. The method may include; forming a hardmask on a strained semiconductor, the strained semiconductor is on a substrate; relaxing edges of the strained semiconductor by forming first trenches through the hardmask and through the strained semiconductor; forming barrier layers in the first trenches; forming a second trench between adjacent barrier layers; and growing a second semiconductor layer on the strained semiconductor having relaxed edges.

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  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cheng, Kangguo Schenectady, US 3073 29791
Hashemi, Pouya White Plains, US 600 4483
Khakifirooz, Ali Los Altos, US 842 11906
Reznicek, Alexander Troy, US 1408 11211

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