High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly
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United States of America Patent
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May 24, 2016
Grant Date -
May 21, 2015
app pub date -
Mar 13, 2013
filing date -
Dec 1, 2010
priority date (Note) -
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status (Latency Note)
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Abstract
A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
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