Single stage latency combined multiplexer and latch circuit
Number of patents in Portfolio can not be more than 2000
United States of America Patent
Stats
-
May 24, 2016
Grant Date -
N/A
app pub date -
Sep 24, 2015
filing date -
Sep 24, 2015
priority date (Note) -
In Force
status (Latency Note)
Importance
Abstract
A combined multiplexer and latch circuit is provided that has only a single gate delay between the input of the overall circuit and the output of the circuit. Two complementary input signal stages each receive a complementary input signal and a multiplexer input. A clocked preset circuit presets a signal at the output of the combined multiplexer and latch circuit with timing based on a first phase of an input clock. A storage circuit stores a value based on the output of the combined multiplexer and latch circuit with timing based on a second phase of the input clock. The circuit has a preset mode during which the output of the combined multiplexer and latch circuit is preset, and has a latch mode during which a value output by the selected complementary signal input stage is output by the circuit and also stored in the storage circuit.
First Claim
Family
International Classification(s)
- [Classification Symbol]
- [Patents Count]
Cited Art Landscape
Patent Citation Ranking
Advertisement
Advertisement
Advertisement
Recipient Email Address
Recipient Email Address
Comment
Recipient Email Address
Add to Portfolio(s)
To add this patent to one, or more, of your portfolios, simply click the add button.
This Patent is in these Portfolios:
Add to additional portfolios:
Last Refreshed On:
Changes done successfully