Pipelined interpolating sub-ranging SAR analog-to-digital converter
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United States of America Patent
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May 31, 2016
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app pub date -
Aug 3, 2015
filing date -
Dec 30, 2014
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Abstract
A multi-bit per cycle successive approximation register (SAR) analog-to-digital converter (ADC) may sample an input signal, successively approximate the sampled signal with a shrinking sub-range containing the signal, and output coarse digital codes corresponding to the sub-range. A sub-ranging stage may continue quantization over the sub-range by sampling and interpolating between a pair of zero crossing signals that bound the sub-range. The zero crossing signals may be taken from the SAR preamp output. The sub-ranging process may be pipelined recursively in multiple stages to increase throughput and efficiency.
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