Shared counter circuit with low-voltage signal output for a column-parallel single slope ADC
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United States of America Patent
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May 31, 2016
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N/A
app pub date -
Mar 27, 2015
filing date -
Mar 27, 2015
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Abstract
A shared counter circuit for a column-parallel single-slope ADC includes an n-bit counter; n low-voltage (LV) drivers connected to receive respective counter output bits and to provide a logic high or logic low output signal which tracks the received bit, the voltage difference between the logic high and logic low output signals being less than Vdd; and a plurality of sets of regenerative latches powered by a supply voltage Vdd, each of which receives an output from a respective LV driver and latches and regenerates the received output as a rail-to-rail CMOS signal upon the occurrence of a trigger event. One typical trigger event occurs when a periodic ramp voltage exceeds an input voltage provided to the ADC which may originate, for example, from the columns of a photodetector array.
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