Testing of LDMOS device

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United States of America Patent

PATENT NO 9362388
SERIAL NO

13208204

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Abstract

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A method for testing an LDMOS transistor by measuring leakage current between the source and drain in the presence of a bias voltage. The leakage current is indicative of defects in the structure of the transistor.

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Patent Owner(s)

Patent OwnerAddress
VOLTERRA SEMICONDUCTOR CORPORATION47467 FREMONT BOULEVARD FREMONT CA 94538

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Cassella, Craig Fremont, US 3 24
Zuniga, Marco A Palo Alto, US 83 1809

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