Delay circuit
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United States of America Patent
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Jun 7, 2016
Grant Date -
Jan 21, 2016
app pub date -
Mar 10, 2015
filing date -
Jul 18, 2014
priority date (Note) -
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status (Latency Note)
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Abstract
A delay circuit includes units each of which includes a first delay element having a first input node and a first output node, a second delay element having a second input node and a second output node, and a third delay element between the first and second delay elements. The first output node of a first unit of the units is connected to the first input node of a second unit of the units. The second input node of the first unit is connected to the second output node of the second unit. A signal on the first input node of the first delay element of the first unit is output from the second output node of the second delay element of the first unit through the third delay element of the second unit.
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