Apparatus to reduce idle link power in a platform
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United States of America Patent
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Jun 14, 2016
Grant Date -
Apr 21, 2016
app pub date -
Dec 22, 2015
filing date -
Jul 1, 2011
priority date (Note) -
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Abstract
A system on a chip (SoC) is provided including processing cores and a root complex. The transaction requests are communicated between a root port of the root complex and a device, the root port including electrical idle (EI) exit detect circuitry and a reference clock source. The root port supports a first link state, in which the reference clock source and EI exit detect circuitry of the root port are disabled but a common mode voltage is maintained, and a second link state, in which the reference clock source and EI exit detect circuitry are disabled and the common mode voltage is not maintained. The root port transitions to the first link state based on a service latency requirement of the device being less than a threshold and to the second link state based on the service latency requirement being greater than or equal to the threshold.
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