Processor instruction set for controlling an event source to generate events used to schedule threads

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United States of America Patent

PATENT NO 9367321
APP PUB NO 20080229310A1
SERIAL NO

11717620

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Abstract

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The invention provides a processor comprising: an execution unit, and a thread scheduler configured to schedule a plurality of threads for execution by the execution unit in dependence on a respective runnable status for each thread. The execution unit is configured to execute thread scheduling instructions which manage the runnable statuses. The thread scheduling instructions including at least: one or more source event enable instructions each of which sets an event source to a mode in which it generates an event dependent on activity occurring at that source, and a wait instruction which sets one of said runnable statuses to suspended pending one of the events upon which continued execution of the respective thread depends. The continued execution comprises retrieval of a continuation point vector for the respective thread.

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Patent Owner(s)

Patent OwnerAddress
XMOS LIMITEDALDER CASTLE 10 NOBLE STREET 5TH FLOOR LONDON EC2V7QJ

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
May, Michael David Bristol, GB 32 636

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