Memory with temperature coefficient trimming

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United States of America Patent

PATENT NO 9368212
SERIAL NO

14669705

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Abstract

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A device includes an array of memory cells, a temperature sensor to provide a temperature output, and a circuit. The circuit provides a bias voltage to bias a node of the array of memory cells based on the temperature output, a first voltage component independent of a temperature coefficient of the memory cells, and a second voltage component dependent on the temperature coefficient of the memory cells. The first voltage component is determined at a first temperature and the second voltage component is determined at a second temperature less than the first temperature.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Pan, Feng Fremont, US 266 3527
Tang, Qiang Cupertino, US 189 770

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