Semiconductor integrated circuit capable of controlling test modes without stopping test
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United States of America Patent
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Jun 14, 2016
Grant Date -
Feb 11, 2010
app pub date -
Jun 12, 2009
filing date -
Aug 8, 2008
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Abstract
A semiconductor integrated circuit capable of controlling test modes without stopping testing of the semiconductor integrated circuit is presented. The semiconductor integrated circuit includes a test mode control unit configured to produce, in response to address decoding signals, a plurality of test mode signals of a first group and a plurality of test mode signals of a second group. The test mode control unit selectively inactivates the test mode signals of the first group by providing a reset signal using the test mode signals of the second group. Therefore, the testing time of the semiconductor integrated circuit can be reduced by inactivating the previous test mode using the reset signal and by executing a new test mode without disconnecting the test mode state.
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