Semiconductor memory device
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United States of America Patent
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Jun 14, 2016
Grant Date -
Apr 16, 2015
app pub date -
Feb 12, 2014
filing date -
Oct 15, 2013
priority date (Note) -
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Abstract
This semiconductor memory device comprises a memory cell array that includes: a plurality of first lines; a plurality of second lines intersecting the plurality of first lines; a plurality of memory cells each disposed at an intersection of the plurality of first lines and the plurality of second lines and including a variable resistance element; and a select transistor respectively connected to an end of the plurality of first lines. The select transistor includes a gate electrode, a gate insulating film, and a conductive layer. Moreover, one end of that conductive layer is connected to the end of the first line, and a non-linear resistance layer configured from a non-linear material is connected between the first line and the conductive layer.
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