Low insertion delay clock doubler and integrated circuit clock distribution system using same
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United States of America Patent
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Jun 21, 2016
Grant Date -
Jul 23, 2015
app pub date -
Jan 21, 2014
filing date -
Jan 21, 2014
priority date (Note) -
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Abstract
A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.
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