Sample hold circuit, A/D converter, calibration method of the sample hold circuit, and circuit
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United States of America Patent
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Jun 21, 2016
Grant Date -
Aug 13, 2015
app pub date -
Aug 12, 2013
filing date -
Sep 7, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
There is provided a pipelined A/D converter in which plural stages Stage 1 to Stage N each including an MDAC (i.e., Multiplying DA Converter) are connected. The pipelined A/D converter is configured with a Gain-AMP (12) included in the MDAC for the SPM, MOS transistors (Mx1) and (Mx2) as a differential pair having output ends connected to a sampling capacitor CsI on a subsequent stage, MOS transistors (My1) and (My2) as a load unit connected to the differential pair, a current source (I3) configured to supply a current to the MOS transistors (Mx1) and (Mx2) as the differential pair, and current sources (I1) and (I2) configured to adjust the current flown across the MOS transistors (My1) and (My2) as the load unit.
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