Semiconductor wafer and insulated gate field effect transistor

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United States of America Patent

PATENT NO 9379226
APP PUB NO 20130168735A1
SERIAL NO

13777770

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Abstract

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Provided is a technique capable of realizing an insulated gate (MIS-type) P-HEMT structure with good transistor characteristics such as an improved carrier mobility of a channel layer and a reduced influence from interface states. A semiconductor wafer includes a base wafer, a first crystalline layer, and an insulating layer. The base wafer, the first crystalline layer, and the insulating layer are stacked in the order of the base wafer, the first crystalline layer, and the insulating layer. The first crystalline layer is made of InxGa1-xAs (0.35≦x≦0.43) that can pseudo-lattice-match with GaAs or AlGaAs. The first crystalline layer is usable as a channel layer of a field effect transistor, and the insulating layer is usable as a gate insulating layer of the field effect transistor.

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Patent Owner(s)

  • SUMITOMO CHEMICAL COMPANY, LIMITED

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fukuhara, Noboru Tsukuba, JP 41 195

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