Rewriting symbol address initialization sequences
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United States of America Patent
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Jul 5, 2016
Grant Date -
May 5, 2016
app pub date -
Dec 15, 2014
filing date -
Oct 30, 2014
priority date (Note) -
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Abstract
A system includes a memory to store a linker and one or modules, and a processor, communicatively coupled to the memory. The computer system is configured to recognize a first symbol address initialization sequence in a module. The system determines whether the first symbol address initialization sequence is a candidate for replacement, determines whether to replace the first symbol address initialization sequence with a second symbol address initialization sequence, and replaces the first symbol address initialization sequence with the second symbol address instruction sequence when it is determined to replace the first symbol address initialization sequence with the second symbol address initialization sequence.
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