Self aligned via in integrated circuit

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United States of America Patent

PATENT NO 9385078
SERIAL NO

15064688

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ATTORNEY / AGENT: (SPONSORED)

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Abstract

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A method for forming a via in an integrated circuit comprises patterning a first opening in a first hardmask, the first hardmask disposed on a first organic self-planarizing polymer (OPL) layer, removing an exposed portion of the first OPL layer to define a cavity, removing an exposed portion of a second hardmask in the cavity, removing an exposed portion of a first dielectric layer disposed under the second hardmask to further define the cavity, removing an exposed portion of a first cap layer in the cavity, removing an exposed portion of a second dielectric layer to further define the cavity, removing an exposed portion of a second cap layer to further define the cavity, removing an exposed portion of a liner layer over a second conductive material in the cavity, and depositing a conductive material in the cavity.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION;STMICROELECTRONICS, INC.;TOKYO ELECTRON LIMITED

International Classification(s)

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Feurprier, Yannick Watervliet, US 17 321
Lee, Joe Albany, US 46 356
Liebmann, Lars W Poughquag, US 124 3878
Mignot, Yann Slingerlands, US 119 279
Spooner, Terry A Clifton Park, US 91 1106
Trickett, Douglas M Altamont, US 19 723
Yilmaz, Mehmet Ankara, TR 9 24

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