Timing phase estimation for clock and data recovery
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United States of America Patent
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Jul 5, 2016
Grant Date -
Aug 28, 2014
app pub date -
Feb 26, 2013
filing date -
Feb 20, 2013
priority date (Note) -
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Abstract
In order to initialize the phase of the recovered clock signal used in clock-and-data recovery (CDR) circuitry, the normal, on-line CDR processing is disabled. The sum of the absolute values of analog-to-digital converter (ADC) samples are generated for different clock phases over each unit interval (UI) of the analog signal sampled by the ADC for a specified period of time. The phase corresponding to the maximum sum is selected as the initial phase for the recovered clock signal for enabled, on-line CDR processing, which among other things, automatically updates the clock phase to ensure that the ADC samples the analog signal near the center of each UI.
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