Reset of multi-core processing system
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United States of America Patent
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Jul 12, 2016
Grant Date -
Oct 10, 2013
app pub date -
Dec 29, 2011
filing date -
Dec 29, 2011
priority date (Note) -
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status (Latency Note)
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Abstract
An initialization core may include reset logic that may detect a global reset signal (GRS). The initialization core may generate one or more packets that enable communication with the cores. The initialization core may send reset packets to each of the cores that instruct the cores to perform a reset. In some embodiments, the reset command may power-off the cores. The initialization core may then transmit unreset packets to each of the cores that instruct the cores to perform an unreset and power-on the cores. In some embodiments, the cores may resume operation automatically without receipt of the unreset packet. The transmission of the packets may be staggered (staged) to control the power-on of the processor and enable the processor unit to more slowly increase its power state.
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