Bus-based clock to out path optimization

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United States of America Patent

PATENT NO 9390220
APP PUB NO 20160026746A1
SERIAL NO

14339229

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Abstract

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A place and route technique is provided for a programmable logic device to optimize a delay difference between a bus including a plurality of clock to out paths and a corresponding clock out path.

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Patent Owner(s)

Patent OwnerAddress
LATTICE SEMICONDUCTOR CORPORATION5555 NE MOORE CT HILLSBORO OR 97124

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Yi, Yanhua Cupertino, US 9 24
Zhao, Jun Fremont, US 511 11979

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