Memory with refresh logic to accommodate low-retention storage rows
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United States of America Patent
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Jul 12, 2016
Grant Date -
Oct 2, 2014
app pub date -
Jun 16, 2014
filing date -
Aug 4, 2005
priority date (Note) -
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Abstract
An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.
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