Semiconductor memory and semiconductor memory control method
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United States of America Patent
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Jul 12, 2016
Grant Date -
Dec 12, 2013
app pub date -
Jun 7, 2013
filing date -
Jun 7, 2012
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor memory includes memory cells, word lines connected to gate of memory cells arranged in a row direction, a control circuit which controls the operation of the memory cells. During k-level data writing to a selected cell, the control circuit applies the corrected unselect voltage in accordance with the result of the reading of data from the unselected cell connected to the adjacent word line to the adjacent word line and applies a read voltage to the selected word line to read (k−1)-level data from the selected cell, and the control circuit writes data to the selected cell in accordance with the read (k−1)-level and the k-level data to be written.
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