Memory control device and a delay controller
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United States of America Patent
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Jul 19, 2016
Grant Date -
Feb 4, 2016
app pub date -
Oct 9, 2015
filing date -
Jun 11, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
A memory control device includes a plurality of delay circuits to set a delay value for each terminal of a memory, each of the plurality of delay circuits being connected to a terminal of the memory. Further, the memory control device includes a first register to store a first DLL value output by a delay locked loop circuit, a plurality of second registers to store a first setting value to set the delay value for the each terminal of the memory, each of the plurality of second registers being connected to a delay circuit of the plurality of delay circuits, and a delay controller to calculate a second setting value based on the first DLL value, a second DLL value output by the delay locked loop circuit after the first DLL value, and the first setting value, and to update the first setting value to the second setting value.
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