Structure and method of latchup robustness with placement of through wafer via within CMOS circuitry

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United States of America Patent

PATENT NO 9397010
SERIAL NO

14993243

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Abstract

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A method of manufacturing a semiconductor structure includes: forming a trench in a back side of a substrate; depositing a dopant on surfaces of the trench; forming a shallow trench isolation (STI) structure in a top side of the substrate opposite the trench; forming a deep well in the substrate; out-diffusing the dopant into the deep well and the substrate; forming an N-well and a P-well in the substrate; and filling the trench with a conductive material.

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Patent Owner(s)

Patent OwnerAddress
INTERNATIONAL BUSINESS MACHINES CORPORATIONNEW ORCHARD ROAD ARMONK NY 10504

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Chapman, Phillip F Colchester, US 14 50
Collins, David S Williston, US 40 665
Voldman, Steven H South Burlington, US 229 3648

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