Transistor gate and process for making transistor gate

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9401279
APP PUB NO 20140367804A1
SERIAL NO

13918648

Stats

ATTORNEY / AGENT: (SPONSORED)

Importance

Loading Importance Indicators... loading....

Abstract

See full text

A transistor gate is formed of a stack of layers including a polysilicon layer and a tungsten layer separated by a barrier layer. A titanium layer reduces interface resistance. A tungsten liner reduces sheet resistance. The tungsten liner, a tungsten nitride barrier layer, and the tungsten layer may be formed sequentially in the same chamber.

Loading the Abstract Image... loading....

First Claim

See full text

Family

Loading Family data... loading....

Patent Owner(s)

Patent OwnerAddress
SANDISK TECHNOLOGIES LLCTWO LEGACY TOWN CENTER 6900 NORTH DALLAS PARKWAY SUITE 325 PLANO TX 75024

International Classification(s)

  • [Classification Symbol]
  • [Patents Count]

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Takeguchi, Naoki Yokkaichi, JP 22 147

Cited Art Landscape

Load Citation

Patent Citation Ranking

Forward Cite Landscape

Load Citation

Maintenance Fees

Fee Large entity fee small entity fee micro entity fee due date
3.5 Year Payment $1600.00 $800.00 $400.00 Jan 26, 2020
7.5 Year Payment $3600.00 $1800.00 $900.00 Jan 26, 2024
11.5 Year Payment $7400.00 $3700.00 $1850.00 Jan 26, 2028
Fee Large entity fee small entity fee micro entity fee
Surcharge - 3.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 7.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge - 11.5 year - Late payment within 6 months $160.00 $80.00 $40.00
Surcharge after expiration - Late payment is unavoidable $700.00 $350.00 $175.00
Surcharge after expiration - Late payment is unintentional $1,640.00 $820.00 $410.00