Trench DMOS device with reduced gate resistance and manufacturing method thereof
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United States of America Patent
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Jul 26, 2016
Grant Date -
Nov 19, 2015
app pub date -
Dec 31, 2013
filing date -
Jan 15, 2013
priority date (Note) -
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Abstract
A trench-type DMOS device includes a substrate as a public drain region, an active region and a voltage-dividing ring formed on the substrate, and a first dielectric layer formed on the substrate. Multiple trenches are located on the first dielectric layer, and the trenches extend from the surface of the first dielectric layer into the interior of the substrate. The trenches comprise at least one first trench distributed in the active region and a second trench outside the active region. A gate oxide layer is formed in the trench and polycrystalline silicon is filled to form a gate. The active region further comprises a source electrode region and a P-type heavily doped region under the source electrode region. A second dielectric layer covers the first dielectric layer and the multiple trenches. A metal layer covers the second dielectric layer to form a first electrode region and a second electrode region.
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