Bias-temperature induced damage mitigation circuit
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United States of America Patent
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Jul 26, 2016
Grant Date -
N/A
app pub date -
Mar 10, 2015
filing date -
Mar 10, 2015
priority date (Note) -
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Abstract
A circuit that regulates electrical current flow through an integrated circuit involves a sequencing circuit connected to a clock signal generator, the sequencing circuit configured to, responsive to receiving a clock signal from the clock signal generator, generate a set of sequencing signals that includes a first switching signal, a second switching signal, and a disable signal. The circuit also involves a switching circuit connected to the sequencing circuit, the switching circuit configured to receive the first switching signal and the second switching signal and a current mirror connected to the switching circuit and the sequencing circuit, the current mirror configured to receive an activation signal from a current control logic circuit and to receive the disable signal.
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