Constraining processor operation based on power envelope information
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United States of America Patent
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Aug 2, 2016
Grant Date -
Apr 2, 2015
app pub date -
Sep 27, 2013
filing date -
Sep 27, 2013
priority date (Note) -
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Abstract
In an embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the core. The power controller may include a power envelope control logic to receive a plurality of power envelope parameters and to enable a power consumption level of the processor to exceed a power burst threshold for a portion of a time window. This portion may be determined according to a length of the time window and a duty cycle, where the power envelope parameters are programmed for a system including the processor and include the power burst threshold, the time window, and the duty cycle. Other embodiments are described and claimed.
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