Address generating circuit and address generating method
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United States of America Patent
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Aug 2, 2016
Grant Date -
Jul 3, 2014
app pub date -
Sep 3, 2013
filing date -
Dec 27, 2012
priority date (Note) -
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status (Latency Note)
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Abstract
An address generating circuit according to an embodiment includes a register that maintains a partition address set by a CPU, a comparator that determines whether a designated address designated by the CPU designates the interleaved area or the non-interleaved area, a selection signal generating unit that generates the selection signal based on a least significant bit of the designated address in a case of the interleaved area and generates the selection signal based on a high-order bit other than the least significant bit of the designated address in a case of the non-interleaved area, and a physical address generating unit that generates the physical address acquired by excluding the least significant bit from the designated address in a case of the interleaved area and generates the physical address acquired by excluding the high-order bit from the designated address in a case of the non-interleaved area.
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