Apparatus and method for accelerating operations in a processor which uses shared virtual memory
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United States of America Patent
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Aug 2, 2016
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app pub date -
Mar 30, 2012
filing date -
Mar 30, 2012
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Abstract
An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.
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