Semiconductor device having a reduced area and enhanced yield

Number of patents in Portfolio can not be more than 2000

United States of America Patent

PATENT NO 9406606
APP PUB NO 20150029776A1
SERIAL NO

14336984

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Abstract

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A device includes a first power supply line supplying a first voltage, first, second, and third nodes, a selection circuit connected between the first power supply line and the first node, a first anti-fuse connected between the first node and the second node, and a second anti-fuse connected between the first node and the third node. The second node and the third node are not connected to each other.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

International Classification(s)

Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Fujisawa, Hiroki Tokyo, JP 173 2521

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