Methods, apparatus, instructions, and logic to provide vector address conflict detection functionality
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United States of America Patent
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Aug 9, 2016
Grant Date -
Jul 3, 2014
app pub date -
Dec 29, 2012
filing date -
Dec 29, 2012
priority date (Note) -
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Abstract
Instructions and logic provide SIMD address conflict detection functionality. Some embodiments include processors with a register with a variable plurality of data fields, each of the data fields to store an offset for a data element in a memory. A destination register has corresponding data fields, each of these data fields to store a variable second plurality of bits to store a conflict mask having a mask bit for each offset. Responsive to decoding a vector conflict instruction, execution units compare the offset in each data field with every less significant data field to determine if they hold a matching offset, and in corresponding conflict masks in the destination register, set any mask bits corresponding to a less significant data field with a matching offset. Vector address conflict detection can be used with variable sized elements and to generate conflict masks to resolve dependencies in gather-modify-scatter SIMD operations.
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