Branch-free condition evaluation
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United States of America Patent
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Aug 9, 2016
Grant Date -
Jun 12, 2014
app pub date -
Dec 11, 2012
filing date -
Dec 11, 2012
priority date (Note) -
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Abstract
A compare instruction of an instruction set architecture (ISA), when executed tests one or more operands for an instruction defined condition. The result of the test is stored as an operand, with leading zeros, in a general register of the ISA. The general register is identified (explicitly or implicitly) by the compare instruction. Thus, the result of the test can be manipulated by standard register operations of the computer system. In a superscalar processor, no special “condition code” renaming is required, as the standard register renaming takes care of out-of-order processing of the conditions.
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