Apparatus and control method for hypervisor to obtain faulting instruction
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United States of America Patent
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Aug 9, 2016
Grant Date -
Jun 18, 2015
app pub date -
Dec 13, 2013
filing date -
Dec 13, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
An apparatus for a hypervisor to obtain a faulting instruction, wherein the hypervisor runs between a physical machine including a central processing unit (CPU) and a virtual machine includes a content addressable memory (CAM); a special-purpose register (SPR) which is accessible by the hypervisor; and a control logic circuit with an input terminal connected to the CPU and an output terminal connected to the CAM, the input terminal receiving data from an instruction fetching (IF) stage and a write-back (WB) stage of a CPU instruction pipeline respectively, the output terminal causing instructions from the IF stage of the CPU instruction pipeline to be stored into the CAM and triggering the CAM to output a faulting instruction among the instructions stored therein to the SPR.
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