DRAM retention monitoring method for dynamic error correction

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United States of America Patent

PATENT NO 9411678
SERIAL NO

13828828

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Abstract

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A method of operation in a memory device, comprising storing data in a first group of storage locations in the memory device, storing error information associated with the stored data in a second group of storage locations in the memory device, and selectively evaluating the error information based on a state of an error enable bit, the state based on whether a most recent access to the first group of storage locations involved a partial access.

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Patent Owner(s)

Patent OwnerAddress
RAMBUS INCSAN JOSE CA

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Ellis, Wayne Campbell, US 14 110
Rajan, Suresh Fremont, US 54 1364
Tsern, Ely Los Altos, US 109 3768
Vogelsang, Thomas Mountain View, US 163 1479
Ware, Frederick A Los Altos Hills, US 757 10947

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