Low density parity check circuit

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United States of America Patent

PATENT NO 9411684
APP PUB NO 20150270851A1
SERIAL NO

14218315

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Abstract

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Generally discussed herein are Low Density Parity Check (LDPC) circuit layouts. An example LDPC circuit can include combinational logic and a plurality of memory units. Each of the plurality of memory units can be electrically coupled to each other and the combinational logic, and the plurality of memory units can be situated in a ring-like configuration.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT100 WALL STREET SUITE 1600 NEW YORK NY 10005

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Derouen, Jacob B Thornton, US 1 1
Hess, Benjamin G Loveland, US 1 1
Holt, Joe F Northglenn, US 1 1
Rajgopal, Suresh San Diego, US 26 238

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