Method and apparatus for bitcell modeling

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United States of America Patent

PATENT NO 9411919
APP PUB NO 20160125114A1
SERIAL NO

14531451

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Abstract

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A methodology for the simulation of semiconductor memory devices that exhibits improved accuracy and speed, and the apparatus performing the methodology are disclosed. Embodiments may include determining a state of a bitcell of an integrated circuit (IC) design, determining a first threshold voltage for the bitcell based on the state of the bitcell, and simulating electrical characteristics of the bitcell according to the first threshold voltage to verify the IC design.

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Patent Owner(s)

Patent OwnerAddress
GLOBALFOUNDRIES SINGAPORE PTE LTD60 WOODLANDS INDUSTRIAL PARK D STREET 2 SINGAPORE 738406

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Huang, Zhiqi Singapore, SG 8 7
Lau, Benjamin Singapore, SG 5 34
Nguyen, Bai Yen Singapore, SG 10 16
Tam, Yoke Weng Singapore, SG 5 5

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