Semiconductor memory apparatus, data transmission device, and recording method
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United States of America Patent
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Aug 9, 2016
Grant Date -
Aug 20, 2015
app pub date -
Apr 30, 2015
filing date -
Jul 16, 2012
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor memory apparatus includes a memory and a speed control unit. The speed control unit calculates a time-varying behavior of a permissible value of an accumulated amount of data written in the non-volatile semiconductor memory, where, after a start of a guaranteed period, data is written in the memory at a constant write speed so that the permissible value at an end time of the guaranteed period is equal to a sum of a first capacity and a second capacity. The first capacity is an accumulated amount of data written in the memory. The second capacity is an accumulated amount of data which is writable in the memory in a remaining time of the guaranteed period based on remaining rewritable times of existing blocks. The speed control unit controls a transmission speed of data from a host based on the permissible value.
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