Integrated circuit fabrication

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United States of America Patent

PATENT NO 9412594
SERIAL NO

14855845

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Abstract

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A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

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Patent Owner(s)

Patent OwnerAddress
U S BANK NATIONAL ASSOCIATION AS COLLATERAL AGENT633 WEST FIFTH STREET 24TH FLOOR LOS ANGELES CA 90071

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Freeman, Eric Kuna, US 53 1890
Lee, John Boise, US 256 5844
Liu, Zengtao Boise, US 29 1014
Nielsen, Russell Boise, US 8 381
Tran, Luan C Meridian, US 176 3478

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