3-D stacked and aligned processors forming a logical processor with power modes controlled by respective set of configuration parameters
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United States of America Patent
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Aug 9, 2016
Grant Date -
Oct 24, 2013
app pub date -
Aug 31, 2012
filing date -
Apr 20, 2012
priority date (Note) -
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Abstract
Methods are provided to operate a processor device in one of multiple power operating modes. The processor device comprises first and second processor chips connected in a stacked configuration, and which respectively include first and second processors that operate as a single logical processor. A control system generates control signals and different sets of configuration parameters. A first control signal is generated to input a first set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a first power operating mode wherein the first processor is turned on and the second processor is turned off. A second control signal is generated to input a second set of configuration parameters to the single logical processor, which is utilized to operate the single logical processor in a second power operating mode wherein both the first processor and the second processor are turned on.
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