Trenched gate with sidewall airgap spacer
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United States of America Patent
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Aug 16, 2016
Grant Date -
Aug 4, 2016
app pub date -
Feb 4, 2015
filing date -
Feb 4, 2015
priority date (Note) -
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status (Latency Note)
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Abstract
A method for fabricating a semiconductor device may include receiving a device substrate comprising a channel layer and a source or drain layer, forming a gate trench within the source or drain layer of the device substrate, depositing a gate dielectric layer and one or more additional gate layers onto the bottom and sidewalls of the gate trench, and removing a substantial portion of at least the gate dielectric layer from the sidewalls of the gate trench to form a left and a right sidewall airgap adjacent to the sidewalls of the gate trench. A corresponding semiconductor device may include a device substrate comprising a channel layer and a source or drain layer, a gate trench formed within the source or drain layer of the device substrate and a sidewall airgap formed adjacent to the sidewalls of the gate trench.
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