High-speed readable semiconductor storage device
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United States of America Patent
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Aug 23, 2016
Grant Date -
May 12, 2016
app pub date -
Jan 19, 2016
filing date -
Dec 2, 2011
priority date (Note) -
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Abstract
According to one embodiment, a semiconductor storage device includes a memory cell array and a controller. The memory cell array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The controller writes data having n values (n is natural numbers of 2 or more to k or less) in the second memory cell and simultaneously writes the fourth memory cell, after writing the data having the n values in the first memory cell. When reading the data from the first memory cell, the controller reads data of the first memory cell and the third memory cell which is selected simultaneously with the first memory cell and, changes a read voltage of the first memory cell based on the data read from the third memory cell.
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