Non-volatile semiconductor memory device
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United States of America Patent
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Aug 23, 2016
Grant Date -
Nov 6, 2014
app pub date -
Jul 17, 2014
filing date -
Mar 26, 2012
priority date (Note) -
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Abstract
A non-volatile semiconductor memory device includes a cell array layer including a first wire, a memory cell, and a second wire, and a control circuit. When performing set operation for setting the memory cell to a low resistance state, until a resistance value of the memory cell becomes lower than a predetermined resistance value, the control circuit repeating: applying a first voltage for setting to the memory cell; and a verify read verifying that the resistance value of the memory cell has become lower than the predetermined resistance value. After the verify read, the control circuit applies a second voltage having a different polarity from the first voltage to the memory cell before applying the first voltage that follows.
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