Semiconductor storage device
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United States of America Patent
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Aug 23, 2016
Grant Date -
Jun 11, 2015
app pub date -
Feb 19, 2015
filing date -
Mar 15, 2013
priority date (Note) -
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status (Latency Note)
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Abstract
According to one embodiment, provided is a semiconductor storage device that includes a control circuit to control the voltage that is applied to the memory cell. The control circuit is configured to execute a reset operation that applies a reset voltage of a first polarity to a selected memory cell that is connected to a selected first wire and a selected second wire during a reset operation. The control circuit is configured to execute a cancel operation that applies a cancel voltage of a second polarity that is opposite to the first polarity to an unselected memory cell and at the same time can execute a verify operation that reads out the state of the selected memory cell by applying a readout voltage of the second polarity to the selected memory cell. The cancel voltage and the readout voltage are the same voltage value.
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