Interaction of transactional storage accesses with other atomic semantics

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United States of America Patent

PATENT NO 9430166
APP PUB NO 20140047205A1
SERIAL NO

13650521

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Abstract

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In a processor, an instruction sequence including, in order, a load-and-reserve instruction specifying a read access to a target memory block, an instruction delimiting transactional memory access instructions belonging to a memory transaction, and a store-conditional instruction specifying a conditional write access to the target memory block is detected. In response to detecting the instruction sequence, the processor causes the conditional write access to the target memory block to fail.

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Patent Owner(s)

  • INTERNATIONAL BUSINESS MACHINES CORPORATION

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Inventor(s)

Inventor Name Address # of filed Patents Total Citations
Frey, Bradly G Austin, US 47 924
Guthrie, Guy L Austin, US 268 2171
May, Cathy Ossining, US 42 998
Williams, Derek E Austin, US 214 1774

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